Prabhu Prasad B M, PhD

I am currently working as an Assistant Professor at Indian Institute of Information Technoology Dharwad, India. I have a PhD from SPARK Lab, Dept. of Computer Science and Engineering, National Institute of Technology Karnataka, Surathkal under the supervision of Dr. Basavaraj Talawar`.

My research focuses on the field of Network-on-Chips, FPGAs, Simulation acceleration, High-performance computing.

Email  /  Google Scholar    

• Paper accepted in Computing, ACM TODAES, CSSP.

Publications

Journal

• Prabhu Prasad B M, Khyamling Parane and Basavaraj Talawar An efficient FPGA based Network-on-Chip simulation framework utilizing the Hard blocks, Computing, Springer, 2020, doi:10.1007/s00034-020-01411-z

• Khyamling Parane, Prabhu Prasad B M and Basavaraj Talawar LBNoC- Design of low-latency router architecture with Lookahead Bypass for Network-on-Chip using FPGA ACM Transactions on Design Automation of Electronic Systems (TODAES), ACM, 2020, 25(1), https://doi.org/10.1145/3365994.

• Khyamling Parane, Prabhu Prasad B M and Basavaraj Talawar P-NoC: Performance Evaluation and Design Space Exploration of NoCs for chip multiprocessor architecture using FPGA Wireless Personal Communications, Springer, https://doi.org/10.1007/s11277-020-07529-2

• Prabhu Prasad B M, Khyamling Parane and Basavaraj Talawar Analysis of cache behaviour and software optimizations for faster on-chip network simulations,International Journal of System Assurance Engineering and Management, Springer, 2019, 10(4), 696–712. doi:10.1007/s13198-019-00799-5

• Khyamling Parane, Prabhu Prasad B M and Basavaraj Talawar YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs, Journal of Ciruits Systems and Computers, World Scientific, 2019, 28:12, doi:0.1142/S0218126619502025

• Prabhu Prasad B M, Khyamling Parane and Basavaraj Talawar High-Performance NoC Simulation Acceleration Framework Employing the Xilinx DSP48E1 Blocks, in 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). Hsinchu, Taiwan:IEEE, April 2019.

• Khyamling Parane, Prabhu Prasad B M and Basavaraj Talawar Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA, in 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). Hsinchu, Taiwan:IEEE, April 2019.

• Prabhu Prasad B M, Khyamling Parane and Basavaraj Talawar High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs, in 20th International Symposium on Quality Electronic Design (ISQED). Santa Clara, CA, USA, USA:IEEE, March 2019.

• G S Sangeetha, Vignesh Radhakrishnan, Prabhu Prasad B M , Khyamling Parane and Basavaraj TalawarTrace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA,in 2018 8th International Symposium on Embedded Computing and System Design (ISED). Cochin, India:IEEE, Dec 2018.

• Prabhu Prasad B M, Khyamling Parane and Basavaraj Talawar YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Using FPGAs, in 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID). Pune, India:IEEE, Jan 2018.

• Khyamling Parane, Prabhu Prasad B M, Basavaraj Talawar Cache analysis and software optimizations for faster on-chip network simulations, in 2016 11th International Conference onIndustrial and Information Systems (ICIIS), IIT Roorkee, India:IEEE, Dec 2016.

• Prabhu Prasad B M, Khyamling Parane and Basavaraj Talawar FPGA based simulation acceleration for Network-on-Chips, in INDOSYS 2017. IIT Bombay, India.

• Khyamling Parane, Prabhu Prasad B M and Basavaraj Talawar On-Chip Network Simulation Accelaration Using FPGAs, in 23rd HiPC 2016, Student Research Symposium. Hyderabad, India.